Testing is regarded as one of the most difficult challenges for three-dimensional integrated circuits (3D ICs). In this paper, we want\r\nto optimize the cost of TAM (test access mechanism) and the test time for 3D IC. We used both greedy and simulated annealing\r\nalgorithms to solve this optimization problem. We compare the results of two assumptions: soft-die mode and hard-die mode. The\r\nformer assumes that the DfT of dies cannot be changed, while the latter assumes that the DfT of dies can be adjusted. The results\r\nshow that thermal-aware cooptimization is essential to decide the optimal TAM and test schedule. Blindly adding TAM cannot\r\nreduce the total test cost due to temperature constraints. Another conclusion is that soft-die mode is more effective than hard-die\r\nmode to reduce the total test cost for 3D IC.
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